1. Field of the Invention
The present invention relates to semiconductor circuit devices and a method of fabricating the same and, more particularly, to those including semiconductor devices having a triple-well structure, for example, an active device such as a MOS transistor, a CMOS circuit, and a storage device such as a memory cell array. The present invention also relates to a pattern constructing technique for a mask device serving as an equipment for fabrication of such semiconductor circuit devices.
2. Description of the Background Art
Semiconductor integrated circuit devices, particularly memory devices and the like, are required to reduce the influences of noises from a semiconductor substrate (effect (1)). More specifically, variations in GND potential applied to the substrate varies the back bias potential of a well region of a MOS transistor, varying the threshold value of the transistor accordingly. Thus, such influences must be prevented. Furthermore, memory devices and the like are required to prevent memory cell data destruction resulting from the injection of a minority carrier current from the substrate into storage nodes of basic memory cells (effect (2)).
From the above described viewpoint, it is a common practice for memory devices and the like to employ a triple-well structure wherein an N-type well region produced in a P-type semiconductor substrate completely surrounds a P-type well region of a memory cell array block comprised of an NMOS transistor, thereby accomplishing the effects (1) and (2).
FIG. 22 is a cross-sectional view of a semiconductor device having a conventional triple-well structure as disclosed in Japanese Patent Application Laid-Open No. 3-30468 (1991), for example. As illustrated in FIG. 22, a P-type well region 2P is completely surrounded by an N-type well region 1P produced in a P-type semiconductor substrate 5P. A P-type contact region 3 for supplying the potential level of the P-type well region 2P is formed in a part of the P-type well region 2P which lies between a part of an insulation film 14P adjacent the inner periphery of a sidewall portion 1PW of the N-type well region 1P and a part of the insulation film 14P adjacent a first source/drain region 18P. A potential VBB is supplied from the exterior to the contact region 3 to fix the potential of the P-type well region 2P at the potential VBB. A ground potential GND is supplied to a contact region 4P to fix the potential of the P-type semiconductor substrate 5P at the potential GND.
However, the use of the triple-well structure as shown in FIG. 22 accomplishes the effects (1) and (2) of the above descried triple-well structure but involves the need to provide in the P-type well region 2P the contact region 3 for supplying the potential to the P-type well region 2P in the triple-well structure. This results in the increased chip area of the semiconductor circuit device by the amount of the area occupied by the contact region 3 in the conventional triple-well structure as represented in FIG. 22.
Additionally, in the conventional triple-well structure as shown in FIG. 22, the contact region 3 must be positioned at a peripheral position offset from the center toward the sidewall portion 1PW in the P-type well region 2P for structural reasons. Then, uniform supply of the potential throughout the P-type well region 2P is not insured.
More high-capacity DRAMs have been constructed such that a memory cell array is divided into sub-arrays for low power consumption and high speed operation. In such a case, a divided word line structure comprised of main word lines and sub-word lines is sometimes employed as an example of word line structures to increase the operating speed of word drivers. In a semiconductor integrated circuit device having such a divided word line structure, if sub-decode circuits for the sub-word lines are comprised of CMOS circuits and located around a memory cell array sub-block, the memory cell array sub-block is surrounded by N-type well regions for PMOS transistors since sense amplifier circuit bands and sub-decode circuit bands positioned to surround the memory cell array sub-block are comprised of CMOS circuits. Such a construction makes it extremely difficult to position the contact region for supplying the potential of the P-type well region of the memory cell array sub-block within the memory cell array sub-block. As a result, the conventional triple-well structure fails to be applied to the semiconductor integrated circuit device having the divided word line structure.
Japanese Patent Application Laid-Open No. 2-196460 (1990) proposes a conventional triple-well structure similar to that illustrated in FIG. 22 for decreasing the area occupied by a chip to reduce the size of a CMOS transistor. This technique, however, is not effective to solve the above described problems approached by the present invention since a P-type contact layer for supplying a fixed potential VSS is formed in an upper corner portion of a P-type well region immediately under each region of the transistor as illustrated in FIG. 1 of the above described reference. Additionally, this technique employs the conventional N-type well region with one sidewall portion thereof completely removed in place of the N-type well region completely surrounding the P-type well region. Then, one side surface of the P-type well region is entirely connected to a P-type substrate. This structure increases the minority carrier current injected from the substrate, creating the new problem of losing the great majority of the original functions and effects of the triple-well structure.
Therefore, the technique disclosed in Japanese Patent Application Laid-Open No. 2-196460 (1990) is not practicable.